Click ~Clock: Rethinking Digital Design Beyond the Clock

This week, Vishwa Eswaran, an associate from the ASIC Team hosted a technical workshop which introduced asynchronous circuits to the larger ECE undergrad community here at UofT on behalf of the ASIC Team. The workshop was held in BA1240 from 6-8PM on October 9th, 2025.

The workshop description was:

Conventional digital design relies on a global clock - a bottleneck for speed, power, and scalability. Asynchronous (clock-free) systems replace it with local handshakes, enabling faster, leaner, and more adaptable hardware. This workshop introduces Async fundamentals and their role in AI, edge, and low-power design, showing how “click not clock” thinking is reshaping next-gen computing.

More than 40 students RSVPd to attend the workshop, which included an interactive portion to demonstrate the potential benefits of asynchronous pipelining.

The workshop slides can be found here, and an open discussion async-circuits channel can be found on our IEEE UofT Discord (Which you can find the invite for on our linktree).

We attempted to record the workshop session, unfortunately technical difficulties got the better of us and we were unable to retrieve the full recording. The first half of the workshop is on youtube, attached to this post.